![]() # Fatal error in Process line_49 at E:/vhdl_Code/testing_sim.vhd line 86Īlthough i'ven't set any of the values to zero. # ** Fatal: (vsim-3977) Integer divide by zero. I tried to make them 32 only but i got this error # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.Īnd simulation stops at a line that i'm dividing 2 variables, each of size (32*2) std_logic_vector, i'm converting them into integer value using conv_integer() function to apply division operation # Time: 100 ns Iteration: 0 Instance: /testing_sim # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 100 ns Iteration: 0 Process: /testing_sim/line_49 File: E:/vhdl_Code/testing_sim.vhd # ** Failure: ARG is too large in CONV_INTEGER # Expect performance to be quite adversely affected.Īfter forcing the input signals to its proper value. # ** Warning: Design size of 18505 statements or 1 leaf instances exceeds ModelSim PE Student Edition recommended capacity. I don't know what to do to make it "uuuuu." and accept binary value.īeside that i'm getting this warning when start simulation I.e at the wave window, when i right click my input port and choose force, "32'hXXXXXXXX" is wrote in the value field. duration, model size, host platform performance, and can be intentional (Modelsim-Altera Starter Edition - the paid version is 33 percent faster). I'm trying to simulate my vhdl file using modelsim but actually it is taking the input value in hex format. Slow simulation comes from the number of events (clock speed) vs.
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